HW-V5-ML501-UNI-G【PDF 25/42 页】EVALUATION PLATFORM VIRTEX-5

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Detailed Description

11. Stereo AC97 Audio Codec

The ML501 board has an AC97 audio codec (U16) to permit audio processing. The Analog

Devices AD1981 Audio Codec supports stereo 16-bit audio with up to 48-kHz sampling.

The sampling rate for record and playback can be different.

Note: The reset for the AC97 codec is shared with the reset signal for the flash memory chips and

is designed to be asserted at power-on or at system reset.

Separate audio jacks are provided for Microphone, Line In, Line Out, and Headphone. All

jacks are stereo except for Microphone. The Headphone jack is driven by the audio codec's

internal 50-mW amplifier. The SPDIF jack supplies digital audio output from the codec.

Table 1-12 summarizes the audio jacks.

Table 1-12:

Reference

Designator

P10

P11

P12

P13

P14

ML501 Audio Jacks

Function

Microphone - In

Analog Line - In

Analog Line - Out

Headphone - Out

SPDIF - Out

12. RS-2 3 2 Serial Port

The ML501 board contains one male DB-9 RS-232 serial port, allowing the FPGA to

communicate serial data with another device. The serial port is wired as a host (DCE)

device. Therefore, a null modem cable is normally required to connect the board to the

serial port on a computer. The serial port is designed to operate up to 115200 Bd. An

interface chip is used to shift the voltage level between FPGA and RS-232 signals.

Note: The FPGA is connected only to the TX and RX data pins on the serial port. Therefore, other

RS-2 3 2 signals, including hardware flow-control signals, are not used. Flow control should be

disabled when communicating with a computer.

A secondary serial interface is available by using header J30 to support debug of the USB

controller chip. Header J30 brings out RS-232 voltage level signals for ground, TX data, and

RX data.

1 3 . 16-Character x 2-Line LCD

The ML501 board has a 16-character x 2-line LCD (Tianma TM162VBA6) on the board to

display text information. Potentiometer R87 adjusts the contrast of the LCD. The data

interface to the LCD is connected to the FPGA to support 4-bit mode only. The CPLD is

used to shift the voltage level between the FPGA and the LCD. The LCD module has a

connector that allows the LCD to be removed from the board to access to the components

below it.

Caution! Care should be taken not to scratch or damage the surface of the LCD window.

ML501 Evaluation Platform

UG226 (v1.4) August 24, 2009

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